1. Technical Field
The present invention generally relates to a semiconductor apparatus, and more particularly, to a voltage trimming circuit and method of a semiconductor apparatus.
2. Related Art
A semiconductor apparatus requires various internal voltages VPP, VBB, VCORE, and VBLP depending on the purpose. In general, the semiconductor apparatus generates a reference voltage and then generates an internal voltage from the generated reference voltage. In order to generate a stable internal voltage, the reference voltage must be stably provided at a target level.
However, the reference voltage may have a minute difference from the target level, due to design in which the semiconductor fabrication process environment or process margin is not considered. Therefore, an operation of trimming the reference voltage level is required to adjust the voltage to the target level.
FIG. 1 is a circuit diagram illustrating a voltage trimming circuit 1 used in a conventional semiconductor apparatus.
The trimming circuit 1 includes a reference voltage provider 10, a divided voltage generator 20, and a trimming reference voltage selector 30.
The reference voltage provider 10 may be configured to generate a predetermined reference voltage VREF from an external voltage VDD.
For example, the reference voltage provider 10 includes a constant current source I and a first NMOS transistor N1. The constant current source I is connected to the external voltage VDD and configured to supply a constant current. The first NMOS transistor N1 having a diode-type structure is connected in series between the constant current I and a ground voltage VSS. A voltage applied to the first NMOS transistor N1 by the current supplied from the constant current source I is outputted as the reference voltage VREF.
The divided voltage generator 20 may be configured to generate a plurality of divided voltages Vtrim<0:7> having various voltage levels based on the reference voltage VREF.
For example, the divided voltage generator 20 includes first to third PMOS transistors P1 to P3, second to sixth NMOS transistors N2 to N6, and first to eighth resistors R1 to R8.
The first and second PMOS transistors P1 and P2 and the second and third NMOS transistors N1 and N2 form a current mirror structure. The second NMOS transistor N2 receives the reference voltage VREF through a gate terminal thereof. The fourth NMOS transistor N4 receives a bias voltage VBIAS and controls a bias of the current mirror.
The third PMOS transistor P3 is connected in series to the fifth and sixth NMOS transistors N5 and N6 connected in a diode type to the external voltage VDD, and receives a drain voltage of the second NMOS transistor N3 through a gate terminal thereof. A voltage divided by the fifth and sixth NMOS transistors N5 and N6 is received through a gate terminal of the third NMOS transistor N3.
The first to eighth resistors R1 to R8 are connected in series between the drain terminal of the third PMOS transistor P3 and the ground voltage VSS. Voltages divided by the respective resistors are outputted as the plurality of divided voltages Vtrim<0:7>.
The trimming reference voltage selector 30 may be configured to output the divided voltages Vtrim<0:7> as a trimming reference voltage VREFT in response to a trimming signal TR<0:7>. The trimming reference voltage VREFT may be finally used as a reference voltage or internal voltage inside the semiconductor apparatus.
The trimming reference voltage selector 30 includes a plurality of pass gates. FIG. 1 illustrates a first pass gate PG1 configured to output the divided voltages Vtrim<0:7> as the trimming reference voltage VREFT in response to the trimming signal TR<0:7> and an inverted trimming signal TRB<0:7>.
FIG. 2 is a graph illustrating a temperature characteristic of the voltage trimming circuit 1.
The reference voltage provider 10 provides the reference voltage VREF at a constant level. However, when the temperature changes, the level of the reference voltage VREF changes according to the temperature characteristic of the NMOS transistor N1. Thus, the level change of the reference voltage VREF has an effect on the level of the trimming reference voltage VREF. Therefore, although the reference voltage VREF was trimmed to generate a target-level trimming reference voltage VREFT at a specific temperature, a trimming reference voltage VREFT having a different level from the target-level trimming reference voltage VREFT may be generated when the temperature changes.
Specifically, suppose that the reference voltage VREF was trimmed so that the level of the trimming reference voltage VREFT becomes X, when the temperature is relatively high (temperature A). Then, when the temperature decreases to a temperature B lower than the temperature A, the trimming reference voltage VREFT is not generated at a desired target level Y at the temperature B, but generated at a level Z which is increased according to the diode characteristic.
That is, the conventional voltage trimming circuit can trim the reference voltage level at a specific temperature, but cannot trim the reference voltage level such that the reference voltage has a desired slope depending on the temperature.